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W83194BR-645 Data Sheet WINBOND CLOCK GENERATOR FOR SIS 645/650 CHIPSET
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Publication Release Date: April 13, 2005 Revision 2.1
W83194BR-645
Table of Contents1. 2. 3. 4. 5. GENERAL DESCRIPTION ..........................................................................................................1 FEATURES ..................................................................................................................................1 PIN CONFIGURATION ................................................................................................................2 BLOCK DIAGRAM .......................................................................................................................2 PIN DESCRIPTION......................................................................................................................3 5.1 Crystal I/O ........................................................................................................................3 5.2 CPU, ZCLK, SDRAM, PCI Clock Outputs .......................................................................3 5.3 I2C Control Interface........................................................................................................4 5.4 Fixed Frequency Outputs ................................................................................................4 5.5 Power Management Pins.................................................................................................5 5.6 Power Pins.......................................................................................................................5 FREQUENCY SELECTION BY HARDWARE OR SOFTWARE .................................................7 I2C CONTROL AND STATUS REGISTERS ................................................................................9 7.1 Register 4: Frequency Select Register (default = 0) .......................................................9 7.2 Register 5: CPU, SDRAM Clock Register (1 = Enable, 0 = Stopped).............................9 7.3 Register 6 PCI Clock Register (1 = Enable, 0 = Stopped) ............................................11 7.4 Register 7 48 MHz, ZCLK, REF Clock Register (1 = Enable, 0 = Stopped)..................11 7.5 Register 8: AGP Control Register (1 = Enable, 0 = Stopped) .......................................11 7.6 Register 9: Watchdog Control Register .........................................................................13 7.7 Register 10: Watchdog Timer Register .........................................................................13 7.8 Register 11: M/N Program Register...............................................................................14 7.9 Register 12: M/N Program Register...............................................................................14 7.10 Register 13: Spread Spectrum Programming Register .................................................14 7.11 Register 14: Divisor and Step-less Enable Control Register.........................................15 7.12 Register 15: CPU_ZCLK Skew Control Register...........................................................15 7.13 Register 16: CPU_AGP_SKEW.....................................................................................15 7.14 Register 17: Skew Control Register...............................................................................16 7.15 Register 18: Winbond Chip ID Register (Read Only) ....................................................16 7.16 Register 19: Winbond Chip ID Register (Read Only) ....................................................16 7.17 Ratio Selection Table.....................................................................................................17 ACCESS INTERFACE ...............................................................................................................19 8.1 Block Write Protocol ......................................................................................................19 8.2 Block Read Protocol ......................................................................................................19 8.3 Byte Write Protocol ........................................................................................................19 8.4 Byte Read Protocol ........................................................................................................19 ORDERING INFORMATION......................................................................................................20 HOW TO READ THE TOP MARKING.......................................................................................20 PACKAGE DRAWING AND DIMENSIONS...............................................................................21 REVISION HISTORY .................................................................................................................22 - II -
6. 7.
8.
9. 10. 11. 12.
W83194BR-645
1. GENERAL DESCRIPTION
The W83194BR-645 is a Clock Synthesizer for SiS645/650 chipset. W83194BR-645 provides all clocks required for high-speed Intel Pentium 4, and also provides 32 different frequencies of CPU clocks frequency setting. All clocks are externally selectable with smooth transitions. The W83194BR645 makes SDRAM in synchronous or asynchronous frequency with CPU clocks. The W83194BR-645 provides step-less frequency programming by controlling the VCO freq. and the programmable AGP, PCI clock output divisor ratio. A watchdog timer is quipped and when time out, register9 bit5 will be set to 1 for warning. Spread spectrum built in at 0.5% or 0.25% to reduce EMI. Programmable stopping individual clock outputs and frequency selection through I2C interface The W83194BR-645 accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply. High drive PCI CLOCK outputs typically provide greater than 1V /nS slew rate into 30 pF loads. The fixed frequency outputs as REF, 24 MHz, and 48 MHz provide better than 0.5V /nS slew rate.
2. FEATURES
* * * * * * * * * * * * * * Supports Intel Pentium 4 CPU with I2C. 2 pairs of differential CPU clocks 2 ZCLK for SiS 645/650 chipset 2 AGP clocks 1 SDRAM output clock for chipset 8 PCI synchronous clocks 1 24/48 MHz, 1 48 MHz 3 REF clocks Skew --- CPU to SDRAM < 1 nS, PCI to PCI < 500 pS, AGP to AGP < 175 pS Smooth frequency switch with selections from 66 to 200 MHz I2C 2-Wire serial interface and I2C read back Flexible spread spectrum to reduce EMI Programmable registers to enable/stop each output and select modes (Mode as Tri-state or Normal) Packaged in 48-pin SSOP
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Publication Release Date: April 13, 2005 Revision 2.1
W83194BR-645
3. PIN CONFIGURATION
VDDR FS0&/REF0 FS1&/REF1 FS2&/REF2 GND XIN XOUT GND ZCLK0 ZCLK1 VDDZ PCI_STOP#* VDDPCI FS3&/PCICLK_F0 FS4&/PCICLK_F1 PCICLK0 PCICLK1 GND VDDPCI PCICLK2 PCICLK3 PCICLK4 PCICLK5 GND &: pull-down 120K * : pull-up 120K # :input active low 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VDDSD SDRAM GND CPU_STOP#* CPUCLKT_1 CPUCLKC_1 VDDC GND CPUCLKT_0 CPUCLKC_0 IREF GND VDDA SDCLK* SDATA* PD#*/VTT_PWGD GND AGPCLK0 AGPCLK1 VDDAGP VDD48 48MHZ 24_48MHZ/ MULTISEL* GND
4. BLOCK DIAGRAM
Driver 48MHz
PLL2
1/2
Mux
24_48MHz
XIN XOUT
XTAL OSC VCOCLK
3
REF0:2
PLL1 Spread Spectrum
Divider
3
Stop
3
CPUCLK_T 0:2 CPUCLK_C 0:2
M/N/Ratio S.S.P ROM
VTT_PWGD FS<4:0> Latch & POR Stop
SDRAM
2
ZCLK 0:1
2
AGPCLK 0:1
8
PCICLK_F0:1 PCICLK_0:5
PD#* PCI_STOP#* CPU_STOP#* MULTISEL0*
Control Logic & Config Register
Rref I2C interface
*SDATA *SDCLK
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W83194BR-645
5. PIN DESCRIPTION
BUFFER TYPE SYMBOL DESCRIPTION
IN INtp120k INtd120k OUT OD I/O I/OD # * &
Input Latched input at power up, internal 120 K pull up. Latched input at power up, internal 120 K pull down. Output Open Drain Bi-directional Pin Bi-directional Pin, Open Drain. Active Low Internal 120 K pull-up Internal 120 K pull-down
5.1 Crystal I/O
PIN PIN NAME TYPE DESCRIPTION
6 7
XIN XOUT
IN OUT
Crystal input with internal loading capacitors (18pF) and feedback resistors. Crystal output at 14.318 MHz nominally with internal loading capacitors (18pF).
5.2 CPU, ZCLK, SDRAM, PCI Clock Outputs
PIN PIN NAME TYPE DESCRIPTION
40, 39, 44, 43
CPUCLKT_0 CPUCLKC_0, CPUCLKT_1 CPUCLKC_1, SDRAM PCICLK_F0
OUT
True CPU clock output and Complementary CPU clock output. This pin will be stopped by CPU_STOP# SDRAM clock output, which have syn. or asyn. Frequencies as CPU clocks. The clock phase is the same as CPUCLKT_0 and CPUCLKT_1. PCI free running clock during normal operation. Latched input for FS3 at initial power up for H/W selecting the output frequency. Internal 120K pull-down PCI free running clock during normal operation. Latched input for FS4 at initial power up for H/W selecting the output frequency. Internal 120K pull-down Low skew (< 500pS) PCI clock outputs.
47
OUT OUT INtd120k OUT INtd120k OUT
14
FS3& PCICLK_F1
15 16, 17, 20, 21, 22, 23
FS4& PCICLK [0:5]
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W83194BR-645
31, 30 9, 10 AGPCLK [0:1] ZCLK [0:1] OUT OUT AGP clock outputs for AGP. Z clock outputs for chipset.
5.3 I2C Control Interface
PIN PIN NAME TYPE DESCRIPTION
34 35
SDATA* SDCLK*
I/O IN
Serial data of I C 2-wire control interface, Internal 120k pullup. Serial clock of I2C 2-wire control interface, Internal 120k pullup.
2
5.4 Fixed Frequency Outputs
PIN PIN NAME TYPE DESCRIPTION
38
IREF
IN
Deciding the reference current for the CPUCLK pairs. The pin was connected to the precision resistor tied to ground to decide the appropriate current. There are two modes to select different current via power on trapping the Pin 26 (MULTISEL0). The table is show as follows. 3.3V, 14.318 MHz reference clock output. Latched input for FS0 at initial power up for H/W selecting the output frequency. Internal 120K pull-down. 3.3V, 14.318 MHz reference clock output. Latched input for FS1 at initial power up for H/W selecting the output frequency, Internal 120K pull-down. 3.3V, 14.318 MHz reference clock output. Latched input for FS2 at initial power up for H/W selecting the output frequency. Internal 120K pull-down. 24 MHz or 48 MHz selected by Register. MULTISEL0 at initial power up for H/W selecting the current multiplier for CPU outputs. Internal 120K pull-up. 48 MHz output for USB.
REF0 2 FS0& REF1 3 FS1& REF2 4 FS2& 24_48 MHz 26 27
OUT INtd120k OUT INtd120k OUT INtd120k OUT
MULTISEL0* INtp120k 48 MHz OUT
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W83194BR-645
5.5 Power Management Pins
PIN PIN NAME TYPE DESCRIPTION
PD#* 33 VTT_PWGD
IN IN
Power Down pin, if PD# = 0, all clocks are stopped. Power good input signal comes from ACPI with high active. This 3.3V input is level sensitive strobe used to determine FS [4:0] and MULTISEL input are valid and is ready to sample. This pin is high active. CPU clock stop control pin, This pin is low active. Internal 120K pull-up. PCI clock stop control pin, This pin is low active. Internal 120K pull-up.
45 12
CPU_STOP#* PCI_STOP#*
IN IN
5.6 Power Pins
PIN PIN NAME DESCRIPTION
1 11 36 42 29 13,19 48 28 5, 8, 18, 24, 25, 32, 37, 41, 46
VDDR VDDZ VDDA VDDC VDDAGP VDDPCI VDDSD VDD48 GND
Power supply for REF0: 2 3.3V. Power supply for ZCLK 3.3V. Power supply for core logic. 3.3V Power supply for CPUCLK 3.3V. Power supply for AGP outputs. Power supply for PCI outputs. Power supply for SDRAM 3.3V. Power supply for 48/24 MHz outputs. Circuit Ground.
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W83194BR-645
Hardware MULTSEL [1:0] Selects Function Multsel1 Byte 8 bit 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Multsel0 Pin 26 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 Board Target trace/Term Z 50 60 50 60 50 60 50 60 50 60 50 60 50 60 50 60 Reference R, IREF = VDD/(3*Rr) Rr = 221 1% IREF = 5.00 mA Rr = 221 1% IREF = 5.00 mA Rr = 221 1% IREF = 5.00 mA Rr = 221 1% IREF = 5.00 mA Rr = 221 1% IREF = 5.00 mA Rr = 221 1% IREF = 5.00 mA Rr = 221 1% IREF = 5.00 mA Rr = 221 1% IREF = 5.00 mA Rr = 475 1% IREF = 2.32 mA Rr = 475 1% IREF = 2.32 mA Rr = 475 1% IREF = 2.32 mA Rr = 475 1% IREF = 2.32 mA Rr = 475 1% IREF = 2.32 mA Rr = 475 1% IREF = 2.32 mA Rr = 475 1% IREF = 2.32 mA Rr = 475 1% IREF = 2.32 mA Output Current Ioh = 4*IREF Ioh = 4*IREF Ioh = 5*IREF Ioh = 5*IREF Ioh = 6*IREF Ioh = 6*IREF Ioh = 7*IREF Ioh = 7*IREF Ioh = 4*IREF Ioh = 4*IREF Ioh = 5*IREF Ioh = 5*IREF Ioh = 6*IREF Ioh = 6*IREF Ioh = 7*IREF Ioh = 6*IREF Voh @ Z 1.0V @ 50 1.2V @ 60 1.25V @ 50 1.5V @ 60 1.5V @ 50 1.8V @ 60 1.75V @ 50 2.1V @ 50 0.47V @ 50 0.56V @ 50 0.58V @ 50 0.7V @ 60 0.7V @ 50 0.84V @ 60 0.81V @ 50 0.97V @ 60
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W83194BR-645
6. FREQUENCY SELECTION BY HARDWARE OR SOFTWARE
This frequency table is used at power on latched FS [4:0] value or software programming at SSEL [4:0] (Register 4 bit 4 ~ 7, 2). FS4 FS3 FS2 FS1 FS0 CPU (MHz) SDRAM (MHz) ZCLK (MHz) AGP (MHz) PCI (MHz)
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W83194BR-645
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 66.67 100.00 100.00 100.00 100.00 100.00 108.00 100.00 100.00 100.00 100.00 80.00 80.00 95.00 95.00 66.67 105.00 100.90 108.00 100.90 112.00 133.33 133.33 133.33 100.00 100.00 100.00 133.33 100.00 100.00 100.00 130.4 66.67 100.00 200.00 133.33 150.00 125.00 162.1 133.33 200.00 166.67 166.67 133.33 133.33 95.00 126.67 66.67 140.00 100.90 144.00 134.53 149.33 100.00 133.33 166.67 133.00 100.00 166.67 166.67 133.00 100.00 166.67 163.0 66.67 66.67 66.67 66.67 60.00 62.50 64.8 80.00 66.67 62.50 71.43 66.67 66.67 63.33 63.33 50.00 70.00 67.27 72.00 67.27 74.67 66.67 66.67 66.67 80.00 80.00 83.33 83.33 100.00 100.00 100.00 93.2 66.67 66.67 66.67 66.67 60.00 62.50 64.8 66.67 66.67 62.50 83.33 66.67 66.67 63.33 63.33 50.00 70.00 67.27 72.00 67.27 74.67 66.67 66.67 66.67 66.67 66.67 62.50 66.67 66.67 66.67 62.50 65.2 33.33 33.33 33.33 33.33 30.00 31.25 32.4 33.33 33.33 31.25 41.67 33.33 33.33 31.67 31.67 25.00 35.00 33.63 36.00 33.63 37.33 33.33 33.33 33.33 33.33 33.33 31.25 33.33 33.33 33.33 31.25 32.6
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W83194BR-645
7. I2C CONTROL AND STATUS REGISTERS
The Register 0~3 are reserved for external clock buffer (The register No. Is increased by 1 if use byte data read/write protocol)
7.1 Register 4: Frequency Select Register (default = 0)
BIT NAME PWD DESCRIPTION
7 6 5 4 3 2 1
SSEL [3] SSEL [2] SSEL [1] SSEL [0] EN_SSEL SSEL [4] EN_SPSP
0 0 0 0 0 Enable software program FS [4:0]. 0 = Select frequency by hardware. 1= Select frequency by software I2C - Bit 4: 7, 2. Frequency selection bit 4 Enable Spread Spectrum in the frequency table. 0 = Normal 1 = Spread Spectrum enabled Enable reload safe frequency when the watchdog is timeout. 0 = reload the FS [4:0] latched pins when watchdog time out. 1 = reload the safe frequency bit defined at Register 9 bit 4~0. Frequency selection by software via I2C
0 0
0
EN_SAFE_FREQ
0
7.2 Register 5: CPU, SDRAM Clock Register (1 = Enable, 0 = Stopped)
BIT PIN NO. PWD DESCRIPTION
7 6 5 4 3 2 1 0
47 44, 43 40, 39 15 14 4 3 2
1 1 1 X X X X X
SDRAM CPUCLKT/C1 CPUCLKT/C0 FS [4] Read back. FS [3] Read back FS [2] Read back FS [1] Read back FS [0] Read back
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W83194BR-645
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W83194BR-645
7.3 Register 6 PCI Clock Register (1 = Enable, 0 = Stopped)
BIT PIN NO. PWD DESCRIPTION
7 6 5 4 3 2 1 0
15 14 23 22 21 20 17 16
1 1 1 1 1 1 1 1
PCICLK_F1 PCICLK_F0 PCICLK 5 PCICLK 4 PCICLK 3 PCICLK 2 PCICLK 1 PCICLK 0
7.4 Register 7 48 MHz, ZCLK, REF Clock Register (1 = Enable, 0 = Stopped)
BIT PIN NO. PWD DESCRIPTION
7 6 5 4 3 2 1 0
27 26 SEL_24 10 9 4 3 2
1 1 1 1 1 1 1 1
48 MHz 24_48 MHz 24/48 MHz frequency control 1: 24 MHz. 0: 48 MHz. ZCLK1 ZCLK0 REF2 REF1 REF0
7.5 Register 8: AGP Control Register (1 = Enable, 0 = Stopped)
BIT PIN NO. PWD DESCRIPTION
7 6 5
1 1 0
CPUCLKT/C0 Stop control: 0: CPUCLK0 free run 1: CPUCLK0 can stopped by CPU_STOP# CPUCLKT/C1 Stop control: 0: CPUCLK1 free run 1: CPUCLK1 can stopped by CPU_STOP# PCI_F0 Stop control: 0: PCI_F0 free run
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W83194BR-645
1: PCI_F0 can stopped by PCI_STOP#
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W83194BR-645
Register 8: AGP Control Register (1 = Enable, 0 = Stopped), continued
BIT
PIN NO.
PWD
DESCRIPTION
4 3 2 1 0 30 31 MULTISEL0 MULTISEL1
0 1 1 1 0
PCI_F1 Stop control: 0: PCI_F1 free run 1: PCI_F1 can stopped by PCI_STOP# AGP_1 AGP_0 MULTISEL0 trapping pin data read back MULTISEL1 (IREF output control)
7.6 Register 9: Watchdog Control Register
BIT NAME PWD DESCRIPTION
7 6
Reserved EN_WD
0 0
Reserved Enable Watchdog Timer if set to 1. Set to 0, disable watchdog timer. Read this bit will return a counting state. If timer continues down count, this bit will return 1. Otherwise, this bit will return 0. Watchdog Timeout Status. If the watchdog is started and timer down counts to zero, this bit will be set to 1. Clear this bit to logic 0, If set to 1, when the watchdog is restart in the next time. This bit is Read Only.
5 4 3 2 1 0
WD_TIMEOUT SAF_FREQ [4] SAF_FREQ [3] SAF_FREQ [2] SAF_FREQ [1] SAF_FREQ [0]
0 0 0 0 0 0
Watchdog safe frequency bits. These bits will be reloaded into FS [4:0], if the watchdog is timeout and enable reload safe frequency bits.
7.7 Register 10: Watchdog Timer Register
BIT NAME PWD DESCRIPTION
7 6 5 4 3 2 1
WD_TIME [7] WD_TIME [6] WD_TIME [5] WD_TIME [4] WD_TIME [3] WD_TIME [2] WD_TIME [1]
0 0 0 0 1 0 0
Watchdog timeout time. The bit resolution is 250 mS. The default time is 8*250 mS = 2.0 seconds. If the watchdog timer is start, this register will be down count. Read this register will return a down count value.
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W83194BR-645
0 WD_TIME [0] 0
7.8 Register 11: M/N Program Register
BIT NAME PWD DESCRIPTION
7 6 5 4 3 2 1 0
N_DIV [8] TEST2 TEST1 M_DIV [4] M_DIV [3] M_DIV [2] M_DIV [1] M_DIV [0]
1 0 1 0 1 0 1 1
Programmable N divisor value. Bit 7~0 are defined in the Register 12. Test bit 2. Winbond test bit, do not change them. Test bit 1. Winbond test bit, do not change them.
Programmable M divisor value.
7.9 Register 12: M/N Program Register
BIT NAME PWD DESCRIPTION
7 6 5 4 3 2 1 0
N_DIV [7] N_DIV [6] N_DIV [5] N_DIV [4] N_DIV [3] N_DIV [2] N_DIV [1] N_DIV [0]
0
0 1 0 1 1 1 1 Programmable N divisor value bit 7~0. The bit 8 is defined in Register 11.
7.10 Register 13: Spread Spectrum Programming Register
BIT NAME PWD DESCRIPTION
7 6 5 4 3 2 1
SP_UP [3] SP_UP [2] SP_UP [1] SP_UP [0] SP_DOWN [3] SP_DOWN [2] SP_DOWN [1]
0 0 0 1 1 1 1
Spread Spectrum Up Counter bit 3. Spread Spectrum Up Counter bit 2. Spread Spectrum Up Counter bit 1. Spread Spectrum Up Counter bit 0 Spread Spectrum Down Counter bit 3 Spread Spectrum Down Counter bit 2 Spread Spectrum Down Counter bit 1 - 14 -
W83194BR-645
0
SP_DOWN [0]
1
Spread Spectrum Down Counter bit 0
7.11 Register 14: Divisor and Step-less Enable Control Register
BIT NAME PWD DESCRIPTION
7
EN_MN_PROG
0
0: use frequency table 1: use M/N register to program frequency The equation is VCO freq. = 14.318MHz * (N+4)/ M. When the watchdog timer is timeout, this will be clear. In this time, the frequency is set to hardware default latched or safe frequency set by EN_SFAE_FREQ (Register 9 bit 0).
6 5 4 3 2 1 0
RATIO_SEL [4] RATIO_SEL [3] RATIO_SEL [2] RATIO_SEL [1] RATIO_SEL [0] TEST0 Reserved
1 0 0 1 1 0 0
CPU, PCI, AGP, SDRAM, and ZCLK ratio selection. The ratio is shown as following table.
Test bit 0. Winbond test bit, do not change them.
7.12 Register 15: CPU_ZCLK Skew Control Register
BIT NAME PWD DESCRIPTION
7 6 5 4 3 2 1 0
CPU_ZCLK_SKEW [2] Reserved Reserved Reserved Reserved Reserved Reserved Reserved
1 0 1 0 0 1 1 1
CPU to ZCLK SKEW control Reserved
Reserved
7.13 Register 16: CPU_AGP_SKEW
BIT NAME PWD DESCRIPTION
7 6 5 4
Reserved Reserved Reserved CPU_STOP
0 0 0 1
Reserved for Winbond internal use, do not change them Reserved for Winbond internal use, do not change them CPU_STOP pin read back Publication Release Date: April 13, 2005 Revision 2.1
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W83194BR-645
3 2 1 0 PCI_STOP CPU_AGP_SKEW [2] CPU_AGP_SKEW [1] CPU_AGP_SKEW [0] 1 1 0 0 CPU_STOP pin read back CPU to AGP skew.
7.14 Register 17: Skew Control Register
BIT NAME PWD DESCRIPTION
7 6 5 4 3 2 1 0
CPU_ZCLK_SKEW [1] CPU_ZCLK_SKEW [0] CPU_SDRAM_SKEW [2] CPU_SDRAM_SKEW [1] CPU_SDRAM_SKEW [0] CPU_PCI_SKEW [2] CPU_PCI_SKEW [1] CPU_PCI_SKEW [0]
0 0 1 0 0 1 0 0
CPU to AGP skew
CPU to SDRAM skew
CPU to PCI skew
7.15 Register 18: Winbond Chip ID Register (Read Only)
BIT NAME PWD DESCRIPTION
7 6 5 4 3 2 1 0
CHPI_ID [7] CHPI_ID [6] CHPI_ID [5] CHPI_ID [4] CHPI_ID [3] CHPI_ID [2] CHPI_ID [1] CHPI_ID [0]
0
1 1 1 0 1 1 1
Winbond Chip ID. W83194BR-645 is 0x77. Winbond Chip ID. Winbond Chip ID. Winbond Chip ID. Winbond Chip ID. Winbond Chip ID. Winbond Chip ID. Winbond Chip ID.
7.16 Register 19: Winbond Chip ID Register (Read Only)
BIT NAME PWD DESCRIPTION
7 6 5 4
SUB_ID [3] SUB_ID [2] SUB_ID [1] SUB_ID [0]
0 0 0 1
Winbond Sub-Chip ID. The sub-chip ID of W83194BR-645 is defined as 0001b. Winbond Sub-Chip ID. Winbond Sub-Chip ID. Winbond Sub-Chip ID.
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W83194BR-645
3 2 1 0
VER_ID [3] VER_ID [2] VER_ID [1] VER_ID [0]
0 0 0 1
Winbond Version ID. The Version ID of W83194BR-645 is 0001b. Winbond Version ID. Winbond Version ID. Winbond Version ID.
7.17 Ratio Selection Table
Table of CPU, PCI, AGP, SDRAM, and ZCLK clock selection.
Reg14 Bit6 SSEL4 Reg14 Bit5 SSEL3 Reg14 Bit4 SSEL2 Reg14 Bit3 SSEL1 Reg14 Bit2 SSEL0 CPU Ratio SDRAM Ratio ZCLK Ratio AGP Ratio PCI Ratio
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
3 3 4 4 4 4 4 4 4 5 5 5 5 5 5 5 5 5 6 6 6
3 4 2 3 3 3 4 4 4 3 3 3 3 3 4 4 4 4 4 6 6
6 6 6 4 5 6 4 5 6 5 6 6 7 8 7 8 8 10 10 6 8
6 6 6 6 6 6 6 6 6 8 8 6 6 8 10 8 10 10 10 6 8
12 12 12 12 12 12 12 12 12 16 16 12 12 16 20 16 20 20 20 12 16
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W83194BR-645
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W83194BR-645
8. ACCESS INTERFACE
The W83194BR-645 provides I2C Serial Bus for microprocessor to read/write internal registers. In the W83194BR-645 is provided Block Read/Block Write and Byte-Data Read/Write protocol. The I2C address is defined at 0xD2.
Block Read and Block Write Protocol
8.1 Block Write Protocol
8.2 Block Read Protocol
## In block mode, the command code must filled 8'h00
8.3 Byte Write Protocol
8.4 Byte Read Protocol
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W83194BR-645
9. ORDERING INFORMATION
PART NUMBER PACKAGE TYPE PRODUCTION FLOW
W83194BR-645
48-pin SSOP
Commercial, 0C to +70C
10. HOW TO READ THE TOP MARKING
W83194BR-645 28051234 242GED
1st line: Winbond logo and the type number: W83194BR-645 2nd line: Tracking code 2 8051234 2: wafers manufactured in Winbond FAB 2 8051234: wafer production series lot number 3rd line: Tracking code 942 G E D 242: packages made in '2002, week 42 G: assembly house ID; O means OSE, G means GR E: Internal use code D: IC revision All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
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W83194BR-645
11. PACKAGE DRAWING AND DIMENSIONS
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W83194BR-645
12. REVISION HISTORY
VERSION DATE PAGE DESCRIPTION
n.a. 1.0 2.0 2.1 01/08/02 02/24/03 4/13/2005 n.a. All 22
All of the versions before 0.50 are for internal use. Change version and version on web site to 1.0 Update new form Add disclaimer
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.
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27F, 2299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62365998
Taipei Office
9F, No.480, Rueiguang Rd., Neihu District, Taipei, 114, Taiwan, R.O.C. TEL: 886-2-8177-7168 FAX: 886-2-8751-3579
Winbond Electronics Corporation Japan
7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800
Winbond Electronics (H.K.) Ltd.
Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064
Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
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